A Testing Strategy for PLAs
- 1 January 1978
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 326-334
- https://doi.org/10.1109/dac.1978.1585193
Abstract
Programmable Logic Arrays (PLA) are finding increasing use as a cost-effective means to utilize LSI electronics. In this paper, three classes of faults, namely stuck faults, shorts and cross-point defects are defined and characterized in a PLA. The relationship between the test sets and their faults among all three classes are discussed. Finally, an algorithm for generating a test set for all three classes of faults is presented.Keywords
This publication has 3 references indexed in Scilit:
- Hardware Implementation of a Small System in Programmable Logic ArraysIBM Journal of Research and Development, 1975
- Redundancy Testing in Combinational NetworksIEEE Transactions on Computers, 1974
- A New Representation for Faults in Combinational Digital CircuitsIEEE Transactions on Computers, 1972