Negative resistance element for a static memory cell based on enhanced surface generation (MOS devices)

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Abstract
A negative resistance (NR) element for a static memory cell using enhanced surface generation of MOS devices is proposed. Such a memory cell will maintain information with extremely small current information and the control circuitry can be the same as in one-transistor dynamic memories. The mechanism of operation is discussed and some experimental data are presented. It is shown that in order to maintain information in a single static memory cell, the required current can be as low as a few picoamperes. Operating currents are large enough to compensate for leakage currents of storage capacitors in dynamic RAM (DRAM) memories. By adding the proposed circuit in parallel with those capacitors, the dynamic memory can be converted into a static memory requiring no refresh circuit or restoring circuit. In the proposed memory structure, the storage capacitor can be reduced significantly or perhaps even eliminated. This will result in much faster operation in comparison to DRAM memories.