Mapping systolic FIR filter banks onto fixed-size linear processor arrays
- 4 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1244-1247 vol.2
- https://doi.org/10.1109/iscas.1990.112355
Abstract
A technique for mapping systolic finite impulse response (FIR) filter banks onto fixed-size processor arrays is presented. It is based on the time-sharing properties of c-slow circuits. The technique can be further developed to a formalism and holds high potential for automatic realization. It has been applied to the mapping of systolic filter banks onto a fixed-size array of transputers.Keywords
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