A 150 MIPS/W CMOS RISC processor for PDA applications

19 November 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 114-115
https://doi.org/10.1109/isscc.1995.535454

Abstract

This CMOS microprocessor has performance of about 45MIPS at 50 MHz with about 300 mW power dissipation at 3.3 V power supply. It implements about 440 k transistors in a 25 mm/sup 2/ die fabricated by 0.41 /spl mu/m double metal CMOS. It is designed as a core processor for PDA applications, that require high speed graphical operation and digital signal processing functions as well as low power consumption from portability requirements.

Keywords

CMOS PROCESS
REDUCED INSTRUCTION SET COMPUTING
ENERGY CONSUMPTION
CIRCUIT SIMULATION
GROUND PENETRATING RADAR
DH-HEMTS
MODEMS
SIGNAL DESIGN
DIGITAL SIGNAL PROCESSING
REGISTERS

This publication has 1 reference indexed in Scilit:

Power and performance simulator: ESP and its application for 100 MIPS/W class RISC design
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1994