Time constrained allocation and assignment techniques for high throughput signal processing
- 2 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A technique for the allocation of complex application specific datapaths is presented. The technique is especially suited for the synthesis of application specific architectures for high-throughput signal processing applications. Such applications comprise hierarchical compositions of nested loops and condition blocks. A minimum area set of datapaths is allocated and the available cycle budget is automatically distributed over the different blocks of the hierarchy in one global optimization process. Results for a number of real life examples are presented.Keywords
This publication has 5 references indexed in Scilit:
- Module assignment and interconnect sharing in register-transfer synthesis of pipelined data pathsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- A generalized interconnect model for data path synthesisPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Fast prototyping of datapath-intensive architecturesIEEE Design & Test of Computers, 1991
- Cathedral-IIIPublished by Association for Computing Machinery (ACM) ,1991
- Sehwa: a software package for synthesis of pipelines from behavioral specificationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988