A 5 GHz CMOS transceiver for IEEE 802.11a wireless LAN

25 June 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. 1, 92-449
https://doi.org/10.1109/isscc.2002.992954

Abstract

A 5 GHz transceiver comprising the RF and analog circuits of an IEEE 802.11a-complaint WLAN using a 0.25 /spl mu/m CMOS technology occupies 22 mm/sup 2/. The IC has 22 dBm maximum transmitted power, 8 dB overall receive-chain noise figure, and -112 dBc/Hz synthesizer phase noise at 1 MHz offset.

Keywords

TRANSCEIVERS
WIRELESS LAN
CMOS TECHNOLOGY
RADIO FREQUENCY
ANALOG CIRCUITS
CMOS ANALOG INTEGRATED CIRCUITS
INTEGRATED CIRCUIT NOISE
INTEGRATED CIRCUIT SYNTHESIS
NOISE FIGURE
SYNTHESIZERS

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