Optimization of low-noise GaAs MESFET's
- 1 June 1980
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 27 (6) , 1034-1037
- https://doi.org/10.1109/t-ed.1980.19983
Abstract
This paper presents a device design which is an effective way of reconciling the two conflicting requirements for low-noise GaAs MESFET's. Decreasing the effective value of gate length can be achieved, without penalty of increased gate metallization resistance, by the virtue of a proper gate-recess structure. This effect can be explained by the "effective gate length" concept. The pertinent fabrication techniques and the optimal noise-figure expression are given for an optimized structure with illustrated examples.Keywords
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