4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor

1 January 2006

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 1728-1734
https://doi.org/10.1109/isscc.2006.1696229

Abstract

A 1-pipe stage, low-latency, 13 FO4, 64b fixed-point execution unit, implemented in a 65nm SOI CMOS process, allows back-to-back execution of data dependent adds, subtracts, compares, shifts, rotates, and logical operations. A 7-pipe stage, 91 FO4, double-precision floating-point unit allows forwarding of dependent results after 6 cycles in most cases

Keywords

DELAY
PIPELINES
FREQUENCY
LATCHES
ADDERS
CLOCKS
MULTIPLEXING
CIRCUIT SYNTHESIS
PERFORMANCE GAIN
CIRCUIT SIMULATION

This publication has 2 references indexed in Scilit:

FPU Implementations with Denormalized Numbers
IEEE Transactions on Computers, 2005
POWER4 system microarchitecture
IBM Journal of Research and Development, 2002