A high density memory for SoC with a 143MHz SRAM interface using sense-synchronized-read/write

22 December 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 306-307 vol.1
https://doi.org/10.1109/isscc.2003.1234310

Abstract

A high density memory (HDRAM) for SoC with SRAM interface is described. This macro achieves no-wait fast random-cycle operation owing to a sense-synchronized read/write scheme. A 4Mb test device is fabricated in a 0.15/spl mu/m process and achieves 143MHz operation. Its size and standby power are 4.59mm/sup 2/ and 92mW, which are 30% and 4.8%, respectively, of an embedded SRAM macro fabricated identically.

Keywords

RANDOM ACCESS MEMORY
VOLTAGE
TIMING
FLIP-FLOPS
LOGIC CIRCUITS
ENERGY CONSUMPTION
MOSFETS
DELAY EFFECTS
TEMPERATURE SENSORS
CIRCUIT SIMULATION

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