N+ Self-Aligned MESFET for GaAs LSIs

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Abstract
The SAINT (Self-Aligned Implantation for N+-layer Technology) procers can embed n +- layers with very low resistance at a controlled distance from Schottky gate. It has been experimentally ascertained that the SAINT has feasibility for GaAs LSIs with advantages of gain, speed, uniformity and stability. An optimum n +-gate spacing in view of resistance-capacitance trade-off is found by combination of experiments and two-dimensional simulation. Guiding principles for the submicron gate are quantitatively discussed with results of the simulation.

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