A 0.35 μm CMOS 3-880 MHz PLL N/2 clock multiplier and distribution network with low jitter for microprocessors

This publication has 2 references indexed in Scilit:

• PLL/DLL system noise analysis for low jitter clock synthesizer design
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Precise delay generation using coupled oscillators
  IEEE Journal of Solid-State Circuits, 1993