Silicon-on-Insulator Wafer Bonding-Wafer Thinning Technological Evaluations

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Abstract
The realization of wafer-scale Silicon-on-Insulator by Van der Waals wafer bonding and subsequent thinning of one of the wafers is described for 100 mm wafers. The bonding of two silicon wafers is brought about by Van der Waals forces which are found to be sufficiently strong for a tight bond at wafer distances of less than 1 nm. This condition requires wafer surfaces which are extremely flat and free of dust particles. Usually the bonding susceptibility is enhanced by a short polishing step. Van der Waals bonding (dipole bonding) is sufficiently strong to withstand the thinning procedure, but bonding is often enhanced by an anneal step (chemical bonding) before thinning. Four thinning procedures are described: 1. Electroless chemical thinning: Selective etching of highly doped bulk material of an active wafer using an electrochemically controlled HF–HNO3–HAc–H2O etchant down to a low-dope, low etch-rate epilayer. 2. Chemical thinning: Electrochemically controlled chemical etching of p-type bulk material of an active wafer down to a p/n junction, where electrochemical passivation of an n-type silicon epilayer occurs. 3. Thinning down to a tribochemical polish stop: In this technique an active wafer is polished until grooves filled with Si3N4 are encountered. The removal rate then becomes small while SOI remains in the areas between the grooves. 4. Polish without stopper: By adapting the existing optical polishing technology, extreme control of flatness and parallelism of wafer surfaces can be achieved. It then becomes possible to polish homogeneously down to SOI layers a few microns thick over a 100 mm wafer. In procedures 1 and 2 an acceptable surface quality is obtained by applying a final tribochemical polishing step. Experimental results of the four technologies are presented. In these technologies, tribochemical polishing is crucial. The necessity of this polishing technology as an off-line facility is discussed in the broader context of ICs of the future.