An integrated interpolative PCM decoder
- 1 February 1979
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 14 (1) , 20-25
- https://doi.org/10.1109/JSSC.1979.1051137
Abstract
Discusses the technique of time averaging interpolation which provides a means for obtaining telephone quality digital-to-analog conversion using conventional digital integrated-circuit processing. Describes a monolithic circuit that decodes the 8-kHz companded PCM commonly used in voiceband communication systems. The circuit, realized in a standard buried collector bipolar technology, contains 300 integrated injection logic (I/SUP 2/L) gates together with a current-driven resistive ladder network. The performance of the decoder exceeds typical toll network objectives.Keywords
This publication has 3 references indexed in Scilit:
- A Per-Channel A/D Converter Having 15-Segment µ-255 CompandingIEEE Transactions on Communications, 1976
- Interpolative Digital-to-Analog ConvertersIEEE Transactions on Communications, 1974
- A Unified Formulation of Segment Companding Laws and Synthesis of Codecs and Digital CompandorsBell System Technical Journal, 1970