A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS

1 February 2010

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 01936530,p. 388-389
https://doi.org/10.1109/isscc.2010.5433967

Abstract

An 8 b SAR ADC is presented. The 90 nm CMOS prototype achieves an ENOB of 7.8 b at a sampling frequency of 10.24 MS/S. The use of asynchronous dynamic CMOS logic, custom-designed capacitors, an internal common-mode shift and low-leakage design techniques results in a power consumption of 69 ¿W from a 1 V supply. The corresponding FoM equals 30 fJ/Conversion-step and is maintained down to 10 kS/s.

Keywords

SAMPLING METHODS
CLOCKS
ENERGY CONSUMPTION
CMOS LOGIC CIRCUITS
FREQUENCY MEASUREMENT
PARASITIC CAPACITANCE
POWER MEASUREMENT
SWITCHED CAPACITOR NETWORKS
SWITCHES
INVERTERS

This publication has 1 reference indexed in Scilit:

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