An Error-Detecting Binary Adder: A Hardware-Shared Implementation

1 January 1970

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers

Vol. C-19 (1) , 34-38
https://doi.org/10.1109/tc.1970.5008897

Abstract

A design for a binary adder-checker system which employs residue codes to detect any error resulting from a single fixed fault is presented. In an adder, special functional relationships must exist, regardless of the particular logical realization. Consequently, for adders with either serial or parallel carry propagation, the worst possible error can be described precisely. Certain residue codes may then be used to detect that error by means of a simple checking algorithm with a minimnum of extra circuitry.

Keywords

This publication has 4 references indexed in Scilit:

Error-Checking Logic for Arithmetic-Type Operations of a Processor
IEEE Transactions on Computers, 1968
Error Detecting and Correcting Binary Codes for Arithmetic Operations
IEEE Transactions on Electronic Computers, 1960
Residues of Binary Numbers Modulo Three
IEEE Transactions on Electronic Computers, 1959
On Checking an Adder
IBM Journal of Research and Development, 1958