Radiation-hard 16K CMOS/SOS clocked static RAM

1 January 1981

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 616-619
https://doi.org/10.1109/iedm.1981.190160

Abstract

A low-temperature, radiation-hard, 2.21µM channel length, CMOS/SOS process has been developed for a 5V power-supply, 16K clocked static RAM, with a standard six-transistor cell configuration. The well-known edge leakage problem in mesa-isolated N-channel SOS transistors has been eliminated. At V DD of 5V, the 16K RAM has typical access times of 150 nsecs and 110 nsecs with phosphorus doped polysilicon and tantalum silicide gates, respectively; the static power dissipation is 35µW and the operating power is 20 mW at 3 MHz.

Keywords

CLOCKS
READ-WRITE MEMORY
SILICON
CMOS TECHNOLOGY
SPACE TECHNOLOGY
SILICIDES
CMOS PROCESS
RANDOM ACCESS MEMORY
ELECTRIC BREAKDOWN
CONDUCTIVITY

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