A 1.28 Gbps 16*16 CMOS chip set for an output-buffer ATM switch
- 2 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A CMOS chip set for a 1.28-Gb/s 16*16 output buffer ATM switch has been developed. By operating at 160 MHz with 8-b parallel input/output, a line speed of 1.28 Gb/s is achieved. 20.5-Gb/s (1.28 Gb/s*16) time division multiplexing has been realized by the introduction of a time multiplexing serial to parallel converter (TMSPC) that consists of flip-flops and 2-1 selectors in a matrix formation. Two clock drivers are used in a one phase scheme with a minimum of propagation delay. ECL-compatible I/O buffers have been used to handle high-speed signals. All chips are developed using 0.8- mu m double-metal CMOS technology.Keywords
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- Output-buffer switch architecture for asynchronous transfer modePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003