A 1Mb CMOS DRAM with fast page and static column modes

• 1 January 1985
• conference paper
• Published by Institute of Electrical and Electronics Engineers (IEEE)
• Vol. XXVIII, 252-253
• https://doi.org/10.1109/isscc.1985.1156776

Abstract

Keywords

• RANDOM ACCESS MEMORY
• CAPACITORS
• READ-WRITE MEMORY
• VARIABLE STRUCTURE SYSTEMS
• SEMICONDUCTOR DEVICES
• LABORATORIES
• CMOS PROCESS
• COUPLING CIRCUITS
• PULSE CIRCUITS
• LEAKAGE CURRENT