A history model for managing the VLSI design process
- 4 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A history model is proposed to support the dynamic aspects of VLSI design, i.e., the controlled and disciplined sequencing of CAD tool invocations. This model is based on a task specification language, for encapsulating CAD tool invocations, and a novel activity thread, which maintains the history of task invocations and serves as a focus for sharing work results in a cooperative manner. A prototype was built on top of the OCT CAD framework.Keywords
This publication has 4 references indexed in Scilit:
- Design management based on design tracesPublished by Association for Computing Machinery (ACM) ,1990
- Electronic CAD frameworksProceedings of the IEEE, 1990
- Automated design tool execution in the Ulysses design environmentIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
- Design Version ManagementIEEE Design & Test of Computers, 1987