Detection of bridging faults in programmable logic arrays
- 18 June 1992
- journal article
- Published by Institution of Engineering and Technology (IET) in Electronics Letters
- Vol. 28 (13) , 1226-1228
- https://doi.org/10.1049/el:19920774
Abstract
A test set and a testable design for MOS PLAs are proposed. The new design, which modifies a PLA by adding one extra line in the AND plane and one extra line in the OR plane, can detect bridging faults. Furthermore, the design modification requires very low area overhead and is independent of the personality of the PLA under test.Keywords
This publication has 1 reference indexed in Scilit:
- Logic Minimization Algorithms for VLSI SynthesisPublished by Springer Nature ,1984