Methodology for efficiently inserting and condensing test points

Abstract
A technique for eliminating hard-to-test or untestable nodes in CMOS integrated circuits is presented. The technique is characterised by a speed degradation smaller than that introduced by others. Also, efficient methods for inserting and condensing test points in combinational circuits are introduced. The experimental results show that only few test points are needed to dramatically reduce the number of random patterns which are required to achieve very close to 100% fault coverage.

This publication has 0 references indexed in Scilit: