Fault grading FPGA interconnect test configurations
- 25 June 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Conventional fault simulation techniques for FPGAs are very complicated and time consuming. The other alternative, FPGA fault emulation technique, is incomplete, and can be used only after the FPGA chip is manufactured. In this paper, we present efficient algorithms for computing the fault coverage of a given FPGA test configuration. The faults considered are opens and shorts in FPGA interconnects. Compared to conventional methods, our technique is orders of magnitude faster, while is able to report all detectable and undetectable faults.Keywords
This publication has 2 references indexed in Scilit:
- Techniques and Algorithms for Fault Grading of FPGA Interconnect Test ConfigurationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2004
- The Little Data Book 2001Published by World Bank ,2001