A new modulo 2/sup a/+1 multiplier
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 614-617
- https://doi.org/10.1109/iccd.1993.393303
Abstract
This paper presents the design of a new modulo 2/sup a/ + 1 multiplier. It makes use of the redundancy in the binary representation of numbers in the finite integer ring R(2/sup 1/+1), though, unlike in some other designs, code translations are not involved. The use of the periodic properties of powers of two taken modulo 2/sup a/+1 simplifies the result correction process and permits a highly regular circuit structure which is suitable for VLSI implementation. Since the multiplier is almost exclusively composed of full and half adders, it can easily be pipelined with throughput reaching hundreds of megahertz. Such performance should make the implementation very attractive in many DSP applications.Keywords
This publication has 5 references indexed in Scilit:
- Design of a discrete cosine transform circuit using the residue number systemPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Regular VLSI architectures for multiplication modulo (2/sup n/+1)IEEE Journal of Solid-State Circuits, 1991
- The design of dual-mode complex signal processors based on quadratic modular number codesIEEE Transactions on Circuits and Systems, 1987
- Modulo (2n+1) arithmetic logicIEE Journal on Electronic Circuits and Systems, 1978
- A simplified binary arithmetic for the Fermat number transformIEEE Transactions on Acoustics, Speech, and Signal Processing, 1976