Trapping-enhanced temperature variation of the threshold voltage of GaAs MESFET's

1 June 1986

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices

Vol. 33 (6) , 792-798
https://doi.org/10.1109/T-ED.1986.22570

Abstract

Using experimental studies and numerical calculations, we demonstrate that the temperature variation of the threshold voltage in long-gate D-mode ion-implanted GaAs MESFET's (L_{gate} \approx 10µm) is caused by the time-dependent effect of traps in the active layer and, to a small extent, by the variation of the channel-substrate interface depletion region with temperature. In short-gate devices (L_{gate} \le 2µm), the piezoelectric effect (which depends on the relative orientation of the devices on the wafer) also contributes to the shift of the threshold voltage with temperature. The measured values of the threshold voltage deduced by several different techniques in the temperature range from - 160 to 160°C are shown to be in good agreement with numerical calculations.

Keywords

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