A submicron VLSI memory with a 4b-at-a-time built-in ECC circuit

• 1 January 1984
• conference paper
• Published by Institute of Electrical and Electronics Engineers (IEEE)
• Vol. XXVII, 104-105
• https://doi.org/10.1109/isscc.1984.1156602

Abstract

Keywords

• VERY LARGE SCALE INTEGRATION
• ERROR CORRECTION CODES
• CIRCUITS
• CMOS TECHNOLOGY
• PREAMPLIFIERS
• MOSFETS
• VOLTAGE
• MOS DEVICES
• WIRING
• RANDOM ACCESS MEMORY