A new DRAM cell structure, based on a new design concept, and a fabrication technology for DRAMs of 16Mbits and beyond are proposed. The proposed cell, called a transistor on a lateral epitaxial (TOLE) silicon layer cell, can achieve high immunity to alpha-particle-induced soft errors and a low parasitic bit line capacitance. The TOLE cell is produced by a silicon-on-insulator (SOI) fabrication technology newly developed by combining epitaxial lateral overgrowth(1)(ELO) and preferential polishing(2)(PP). Reasonable electrical characteristics for the TOLE transistor and excellent immunity against alpha-particle disturbance for the TOLE memory cell are confirmed.