Test methodology for a microprocessor with partial scan

27 November 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 708-716
https://doi.org/10.1109/test.1998.743215

Abstract

Microprocessors are incredibly complex devices that typically have many non-standard logic, array, and I/O structures. Testing of microprocessors has become an increasingly difficult problem because of these non-standard structures. This paper will discuss the test methodology put in place to test a PowerPC microprocessor which is used in both the AS/400 and RS/6000 computer lines. This microprocessor has a number of features which made test a challenge. These features include partial scan sections of logic, extremely high signal count of nearly 1000 I/O, custom logic designed at the transistor level, and non-scannable arrays not directly accessible from outside the microprocessor.

Keywords

MICROPROCESSORS
LOGIC ARRAYS
LOGIC TESTING
LOGIC DESIGN
COSTS
AUTOMATIC TESTING
SIGNAL DESIGN
SHIFT REGISTERS
PROCESS DESIGN
LIFE TESTING

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