Evaluation of a branch target address cache

This publication has 15 references indexed in Scilit:

• 80960-next generation
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• The PowerPC 601 microprocessor
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• An architecture for high instruction level parallelism
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Branch target buffer design and optimization
  IEEE Transactions on Computers, 1993
• Improving the accuracy of dynamic branch prediction using branch correlation
  Published by Association for Computing Machinery (ACM) ,1992
• Design and implementation trade-offs in the Clipper C400 architecture
  IEEE Micro, 1991
• IBM RISC System/6000 processor architecture
  IBM Journal of Research and Development, 1990
• Available instruction-level parallelism for superscalar and superpipelined machines
  Published by Association for Computing Machinery (ACM) ,1989
• Branch Prediction Strategies and Branch Target Buffer Design
  Computer, 1984
• The Inhibition of Potential Parallelism by Conditional Jumps
  IEEE Transactions on Computers, 1972