A 120 MFLOPS CMOS floating-point processor

Publisher Website

9 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/cicc.1991.164128

Abstract

No abstract available

Keywords

This publication has 1 reference indexed in Scilit:

A SIGNED BINARY MULTIPLICATION TECHNIQUE
The Quarterly Journal of Mechanics and Applied Mathematics, 1951