A 32-bit RISC Implemented in Enhancement-Mode JFET GaAs
- 1 October 1986
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in Computer
- Vol. 19 (10) , 60-68
- https://doi.org/10.1109/mc.1986.1663072
Abstract
No abstract availableKeywords
This publication has 10 references indexed in Scilit:
- An Introduction to GaAs Microprocessor Architecture for VLSIComputer, 1986
- VLSI Processor ArchitectureIEEE Transactions on Computers, 1984
- Double-implanted GaAs complementary JFET'sIEEE Electron Device Letters, 1984
- Optimizing delayed branchesACM SIGMICRO Newsletter, 1982
- Measurement and analysis of instruction use in the VAX-11/780ACM SIGARCH Computer Architecture News, 1982
- A Regular Layout for Parallel AddersIEEE Transactions on Computers, 1982
- The 801 minicomputerPublished by Association for Computing Machinery (ACM) ,1982
- Hardware/software tradeoffs for increased performancePublished by Association for Computing Machinery (ACM) ,1982
- The case for the reduced instruction set computerACM SIGARCH Computer Architecture News, 1980
- Femtojoule high speed planar GaAs E-JFET logicIEEE Transactions on Electron Devices, 1978