Comments on "An Algorithm for Synthesis of Multiple-Output Combinational Logic"

1 November 1968

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers

Vol. C-17 (11) , 1091-1092
https://doi.org/10.1109/tc.1968.226866

Abstract

—The principal synthesis example of Schneider and Dietmeyer's paper [1] is examined by applying a new synthesis algorithm. The minimum NOR gate realization thus obtained is used to illustrate the nonoptimality of their approach and to question their definition of delay. Arguments are advanced for synthesis with simple modules.

Keywords

DELAY
ARGUMENTS
OUTPUT
COMMENTS
SCHNEIDER
SYNTHESIS ALGORITHM
NONOPTIMALITY
ILLUSTRATE
ABSTRACT&MDASH
DIETMEYER'S

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