A stuck fault model for dynamic CMOS combinational circuits
- 1 January 1991
- journal article
- Published by Elsevier in Microelectronics Reliability
- Vol. 31 (2) , 407-427
- https://doi.org/10.1016/0026-2714(91)90228-y
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- Testing for multiple faults in domino-CMOS logic circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- MOS Test Pattern Generation Using Path AlgebrasIEEE Transactions on Computers, 1987
- NORA: a racefree dynamic CMOS technique for pipelined logic structuresIEEE Journal of Solid-State Circuits, 1983
- Fault Modeling and Logic Simulation of CMOS and MOS Integrated CircuitsBell System Technical Journal, 1978