Vertical isolation in shallow n-well CMOS circuits

1 March 1987

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters

Vol. 8 (3) , 107-109
https://doi.org/10.1109/EDL.1987.26568

Abstract

This letter examines vertical punchthrough in a shallow conventional n-well suitable for use in high-packing-density VLSI CMOS circuits. It is shown that full vertical isolation can be maintained even when the well beneath a p+ diffusion is completely depleted-that is the p+-to-n-well and n-well-to-p-substrate depletion regions meet-and that this offers an advantage in terms of p+ junction capacitance. However, if thin p-on-p+ epitaxial substrate material is used for latch-up suppression, then vertical isolation can be severely degraded. This effect ultimately limits the thickness of the epitaxial layer and hence the degree of latch-up protection.

Keywords

CIRCUITS
SUBSTRATES
EPITAXIAL LAYERS
DOPING PROFILES
VARIABLE STRUCTURE SYSTEMS
VERY LARGE SCALE INTEGRATION
CAPACITANCE
DEGRADATION
PROTECTION
CMOS TECHNOLOGY

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