General algorithms for reduced-adder integermultiplier design

12 October 1995

journal article
Published by Institution of Engineering and Technology (IET) in Electronics Letters

Vol. 31 (21) , 1800-1802
https://doi.org/10.1049/el:19951242

Abstract

The problem of reducing the number of adders required to perform shift-and-add multiplication is addressed for hardware and software applications. Algorithms invented for each of these applications are compared and found to have similar performances in general. Improved results are achieved by selecting the best design of the two.

Keywords

This publication has 6 references indexed in Scilit:

Strength reduction of multiplications by integer constants
ACM SIGPLAN Notices, 1995
Compiler transformations for high-performance computing
ACM Computing Surveys, 1994
Constant integer multiplication using minimum adders
IEE Proceedings - Circuits, Devices and Systems, 1994
Greedy hardware optimization for linear digital circuits using number splitting and refactorization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1993
Experience with a software-defined machine architecture
ACM Transactions on Programming Languages and Systems, 1992
Multiplication by integer constants
Software: Practice and Experience, 1986