Synthesis of low power linear DSP circuits using activity metrics
- 17 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 10639667,p. 265-270
- https://doi.org/10.1109/icvd.1994.282699
Abstract
Power has become an important optimizing parameter due to increasing use of portable and remote electronic systems. In a CMOS circuit, node activity is directly proportional to the amount of power drawn. We analyze activity metrics at high level for adders and multipliers and derive architectural transformations for synthesizing low power circuits. The goal is to identify data flow graph transformations that reduce overall circuit activity rather than accurate prediction of power consumption. It is shown experimentally that the transformations are power-efficient over many classes of input signals applied to several digital signal processing (DSP) test circuits.Keywords
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