CMOS n-well microbolometer FPA with temperature coefficient enhancement circuitry

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Abstract
This paper reports the development of a low-cost CMOS microbolometer focal plane array with a new temperature coefficient enhancement readout circuit. We have recently reported an uncooled microbolometer detector that uses the CMOS n-well layer as the active material, where the suspended and thermally isolated n-well structure is obtained by silicon bulk micromachining of fabricated CMOS dies. In addition, we have successfully fabricated a 16 X 16 n-well microbolometer FPA. Although n-well is single crystal silicon and has very low 1/f noise, the fabricated array performance was limited due to low TCR of the n-well. The n-well has a TCR of 0.50 - 0.70%/K, which is the highest among the CMOS layers, but lower compared to the state-of-the-art microbolometer materials whose TCR values are about 2 - 3%/K. This paper reports a new n-well microbolometer FPA with a readout circuit that enhances the temperature coefficient (TC) of the microbolometer current, compensating for the low TCR value of the detector. The TC enhancement is achieved by passing the pixel current through a 4th power taking circuit prior to integration, increasing the pixel current TC four times and resulting in an effective TC of 2.0 - 2.8%/K. A 16 X 16 test array has been designed and fabricated using a 0.8 micrometers standard CMOS process. The chip measures 2.4 X 3.8 mm2 and contains 80 micrometers X 80 micrometers microbolometer pixels with 13% fill factor. The measurements and calculations show that the 16 X 16 prototype FPA can provide a responsivity (R) of 2 X 107 V/W, a detectivity (D*) of 1.68 X 109 cm(root)Hz/W, and NETD of 290 mK at a scanning rate of 260 fps. The same NETD value can be obtained for a 128 X 128 pixel array operating at 30 fps. NETD can further be decreased by improving the noise performance of the readout circuit, since the performance is not limited by the n-well microbolometer noise.

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