A high-speed architecture for ADPCM codec

2 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. 3, 1499-1502
https://doi.org/10.1109/iscas.1992.230216

Abstract

A pipelined architecture for adaptive pulse code modulation (ADPCM) is presented. The architecture is developed by the application of a realized form of look-ahead. The hardware overhead is only the pipelining latches and is independent of the number of quantizer levels, the predictor order, and the pipelining level. The codec latency is smaller than the level of pipelining. Under the assumption of small quantization error, the convergence properties of the pipelined architecture are compared with those of the serial one. Speech and image coding examples are presented to support the conclusions reached.

Keywords

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