Design Limitations due to Substrate Currents and Secondary Impact lonization Electrons in NMOS LSI's

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Abstract
A quantitative analysis of the substrate current and its secondary effects in NMOS LSI's are described. The substrate current is accurately calculated by a two-dimensional numerical analysis for short channel transistors down to 1 µm channel length. Minority carrier injection in substrate, which results from a secondary impact ionization, is also studied. The minority carrier current in the substrate is measured using a CCD test device, and is found to be nearly proportional to the substrate current. A physical model for these phenomena is also presented. Minority carrier injection efficiency is then given by an empirical equation as a function of effective channel length. Based on the models and experimental results, limiting voltages for MOS LSI's are estimated in terms of punch-through, parasitic bipolar transistor breakdown, excess electrons and hot electron trapping.

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