Representation of Sequential Circuits in Combinatory Logic

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Abstract
We will be dealing with “sequential circuits” in the sense of E. F. Moore and G. H. Mealy. Each such circuit is assumed to have a finite number of input wires (possibly none) and a finite number of output wires (but at least one). Each element of such a circuit will be assumed to be an and-circuit, an or-circuit, a not-circuit, or a delay circuit, for some specified temporal delay. Each element has one output wire which, however, may branch in order to serve several purposes simultaneously. (Similarly the inputs of the total circuit may be allowed to branch.) The and-circuits and or-circuits have two input wires each, while the not-circuits and the delay circuits have one input wire each.

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