21 psec switching 0.1 μm-CMOS at room temperature using high performance Co salicide process
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 01631918,p. 906-908
- https://doi.org/10.1109/iedm.1993.347254
Abstract
In this paper we report a record of 0.1 /spl mu/m-CMOS switching delay of 21 psec per gate at room temperature operation. Good subthreshold characteristics are achieved for 0.1 pm gate length n-MOS and p-MOS. Conventional Ti, Pt and Co self-aligned silicide process (salicide) degraded the 0.1 pm CMOS switching delay because the gate sheet resistances increased at fine-line. In contrast, Co salicide with TiN capping process achieved a low gate resistance of 5 /spl Omegasq at all over gate length. And it allowed the high speed operation at the sub quarter micron gate length region.<>Keywords
This publication has 2 references indexed in Scilit:
- High-performance 0.10- mu m CMOS devices operating at room temperatureIEEE Electron Device Letters, 1993
- A High Performance 0.25/spl mu/m CMOSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993