A precision trim technique for monolithic analog circuits
- 1 December 1975
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 10 (6) , 412-416
- https://doi.org/10.1109/jssc.1975.1050635
Abstract
A technique for permanent adjustment of precision analog circuits at wafer test by selective shorting of Zener diodes is presented. Analytical details of the trimming procedure and a physical description of diode short-circuiting are given. The method is applied to a precision operational amplifier with input offset voltage reduced to 10 /spl mu/V. The necessity of optimizing other related parameters is demonstrated. Practical considerations limiting wafer test accuracy are discussed. Circuit performance is summarized.Keywords
This publication has 2 references indexed in Scilit:
- An improved performance MOS/bipolar op-ampPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1974
- A five-terminal plus or minus 15-V monolithic voltage regulatorIEEE Journal of Solid-State Circuits, 1971