Vectorized model checking for computation tree logic

This publication has 5 references indexed in Scilit:

• Design and synthesis of synchronization skeletons using branching time temporal logic
  Published by Springer Nature ,2005
• What are the limits of model checking methods for the verification of real life protocols?
  Published by Springer Nature ,1990
• Avoiding the state explosion problem in temporal logic model checking
  Published by Association for Computing Machinery (ACM) ,1987
• Automatic Verification of Sequential Circuits Using Temporal Logic
  IEEE Transactions on Computers, 1986
• Automatic verification of finite state concurrent system using temporal logic specifications
  Published by Association for Computing Machinery (ACM) ,1983