A Physical Model for Degradation of DRAMs During Accelerated Stress Aging

1 April 1983

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE) in 8th Reliability Physics Symposium

No. 07350791,p. 90-95
https://doi.org/10.1109/irps.1983.361966

Abstract

Charge trapping and interface-state generation at the Si/SiO2 interface have been characterized from the results of pulse-aging and radiation damage experiments conducted on the n-channel Si-Gate MOSFETs. The detailed analysis indicates that it is the intrinsic property of the Si/SiO2 interface to trap holes which act as Qr-like charges. The holes once they are trapped do not redistribute along the interface, but in presence of hydrogen they move toward Si and convert to fast-interface states (Dit). The degradations of the hold-time and the minimum voltage required to operate of a DRAM are related to the densities of Qf and Di, respectively. The ultimate degradation depends on the resultant of the rate of build-up and the rate of annealing of Qf and Dit.

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