A CMOS RISC CPU with on-chip parallel cache

17 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 210-211
https://doi.org/10.1109/isscc.1994.344666

Abstract

This CMOS CPU in a 0.55 /spl mu/m, 3-metal process integrates over 1.2 M transistors on a single chip. All circuitry on-chip operates at 140 MHz under typical conditions. All off-chip interfaces are cycled at the same frequency (with the exception of system bus interface, which is cycled at 120 MHz). Chip parameters are given.<>

Keywords

REDUCED INSTRUCTION SET COMPUTING
PREFETCHING
COMPUTER AIDED MANUFACTURING
CADCAM
READ-WRITE MEMORY
CIRCUITS
PIPELINES
TIMING
RAILS
CMOS PROCESS

This publication has 2 references indexed in Scilit:

A 30 MIPS VLSI CPU
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
CMOS processor circuit design in Hewlett-Packard's series 700 workstations
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002