Scheme for distributing high-speed clock signals in a large digital system
- 19 January 1989
- journal article
- Published by Institution of Engineering and Technology (IET) in Electronics Letters
- Vol. 25 (2) , 92-93
- https://doi.org/10.1049/el:19890068
Abstract
The details of a clock distribution circuit for a large digital system operating at 250 MHz are presented. The arrangement provides pulse compression control and preserves the clock timing at the 100 ps level even when parts of the circuit are replaced.Keywords
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