Three-dimensional characterization of bipolar transistors in a submicron BiCMOS technology using integrated process and device simulation
- 1 January 1992
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 01631918,p. 923-926
- https://doi.org/10.1109/iedm.1992.307507
Abstract
Results of complete 3-dimensional AC/DC characterizations of the n-p-n transistor in a submicron BiCMOS technology are presented. Accuracy and throughput acceptable for constructing compact models is achieved through the use of multidimensional process simulation, adaptive grid generation and preconditioned iterative techniques for both DC and small-signal analysis. Comparisons of 2- and 3-dimensional simulations with measurements enable assessments of the magnitude of 3-dimensional effects, thereby suggesting efficient device optimization strategies.Keywords
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