ISDN echo cancellation circuit (IEC), a transceiver for the subscriber loop

6 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 853-856
https://doi.org/10.1109/iscas.1988.15057

Abstract

The digital part of a two-chip U-interface transceiver for the subscriber loop is presented. According to the ISDN (integrated-services digital network) standard all communication control and algorithmic requirements are implemented for a 144-kb/s full duplex data transmission. The chip is implemented in a double-metal 2- mu m CMOS technology with an area of 8.2 mm*7.3 mm containing 58000 transistors, 15000 of which are implemented in a cell approach, the rest in hand-tuned digital signal processor.

Keywords

ISDN
ECHO CANCELLERS
CIRCUITS
IEC
TRANSCEIVERS
CMOS TECHNOLOGY
SUBSCRIBER LOOPS
COMMUNICATION STANDARDS
COMMUNICATION SYSTEM CONTROL
SIGNAL PROCESSING ALGORITHMS

This publication has 1 reference indexed in Scilit:

ISDN-Oriented Modular VLSI Chip Set for Central-Office and PABX Applications
IEEE Journal on Selected Areas in Communications, 1986