Damascene-gate thin film transistors

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Abstract
Amorphous silicon thin film transistors (TFTs) currently used in active-matrix liquid crystal displays are bottom-gate structures. This introduces the problem of step coverage over the gate. Specifically, a thick gate dielectric is required to adequately cover the gate metal in order to prevent leakage current between the gate and the source/drain, however, it is preferable to minimize the thickness of the gate dielectric in order to reduce the threshold voltage, V/sub T/, and the sub-threshold slope, S. The approach presented in this paper is to embed the gate metal into a trench made into a passivating layer above the substrate so that the top of the gate metal is level with the surface of the passivation layer. Such a structure has several key advantages: (1) reduces gate line resistance by allowing for thick gate lines; (2) does not increase gate line capacitance since there is no increase in effective area; (3) allows the use of low-resistivity metals such as copper, which would be encapsulated by the nitride sidewalls and a metal cap-layer; and (4) permits the use of thin gate dielectrics (<200 nm).

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