Improved Compaction by Minimized Length of Wires
- 1 January 1983
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 0738100X,p. 121-127
- https://doi.org/10.1109/dac.1983.1585636
Abstract
The compaction of IC or hybrid layouts by means of the "longest path" method yields a slack in the placement of part of the elements, which, in its turn, can be used to reduce the overall wire-length. The result is an improved electrical performance and a smaller layout. The optimization problem was transformed to a graph-theoretical problem in a way similar to the compaction problem itself. Our procedure starts by adding pieces of information out of the connectivity of the layout to the constraint graph. The succeeding heuristic algorithms generate a new tree of longest paths, taking the linear inequalities and the result of the longest path calculation into consideration. A few examples demonstrate the significant reduction of wire-length and sometimes even an additional reduction of layout area achieved with low computational effort.Keywords
This publication has 3 references indexed in Scilit:
- ALI: A Procedural Language to Describe VLSI LayoutsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982
- An analytical method for compacting routing area in integrated circuitsPublished by Association for Computing Machinery (ACM) ,1982
- SLIP: symbolic layout of integrated circuits with compactionComputer-Aided Design, 1978