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High Level Synthesis of ASICs under Timing and Synchronization Constraints
Home
Publications
High Level Synthesis of ASICs under Timing and Synchronization Constraints
High Level Synthesis of ASICs under Timing and Synchronization Constraints
DK
David C. Ku
David C. Ku
GM
Giovanni Micheli
Giovanni Micheli
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1 January 1992
book
Published by
Springer Nature
https://doi.org/10.1007/978-1-4757-2117-1
Abstract
No abstract available
Keywords
ASIC
HARDWARE
SIGNAL
ALGORITHMS
COMMUNICATION
COMPLEXITY
COMPUTER
INTEGRATED CIRCUIT
LOGIC
MODEL
MODELING
OPTIMIZATION
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Cited by 83 articles
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